Boardadafruit

Adafruit Feather ESP32-S3

Adafruit Feather ESP32-S3: the standard Feather header around an ESP32-S3 mini-module: 28 through-holes in two columns, JP1 left (16 holes, pin 16 RESET at the top, pin 1 TXD0/GPIO43 at the bottom) and JP3 right (12 holes, pin 1 VBAT at the top, pin 12 SDA at the bottom), NeoPixel on GPIO33 (power-gated by GPIO21), I2C on GPIO3/4 with a STEMMA QT connector switchable through GPIO7, MAX17048 fuel gauge, native USB-C. Three SKUs (5323/5477/5885) share one schematic.

Assembly & compatibility

Main chip: ESP32-S3

Revisions

Current production board — One PCB revision covers all three SKUs; 'v1' is an internal ordering id, the vendor publishes no revision letter. · Adafruit Feather ESP32-S3 PCB repo (PrettyPins pinout PDF, Eagle schematic, Fab Print; commit 2025-09-10) · Adafruit Feather ESP32-S3 Pinout.pdf

Pinout

power · ground · GPIO / signal · onboard LED

Left header column (component face, USB up), 16 through-holes; pin 16 (RESET) at the top, pin 1 (TXD0) at the bottom (16 pins)

TXD0 (JP1.1) is the ESP32-S3 native UART0 TX on GPIO43 - a distinct hole from the Feather 'TX' pad (JP1.2, GPIO39); JP1.14 and JP1.15 are both 3.3V (same net, two positions) · Source: Adafruit Feather ESP32-S3 PCB repo (PrettyPins pinout PDF, Eagle schematic, Fab Print; commit 2025-09-10) · feather-esp32s3.brd @2c95ed5 signal netlist, element JP1 (HEADER-1X16_ROUND)

No.	Name	Type	GPIO	Function
1	TXD0	O	43	GPIO43; native UART0 TX (U0TXD)
2	TX	I/O	39	GPIO39 (MTCK); Feather UART TX
3	RX	I/O	38	GPIO38 (FSPIWP); Feather UART RX
4	MISO	I/O	37	GPIO37 (FSPIQ)
5	MOSI	I/O	35	GPIO35 (FSPID)
6	SCK	I/O	36	GPIO36 (FSPICLK)
7	A5	I/O	8	GPIO8; ADC1_CH7
8	A4	I/O	14	GPIO14; ADC2_CH3
9	A3	I/O	15	GPIO15; ADC2_CH4
10	A2	I/O	16	GPIO16; ADC2_CH5
11	A1	I/O	17	GPIO17; ADC2_CH6
12	A0	I/O	18	GPIO18; ADC2_CH7
13	GND	G		Ground
14	3.3V	P		3.3 V output from the regulator
15	3.3V	P		3.3 V output (same net as pin 14)
16	RESET	C		ESP32-S3 EN / reset

Right header column (component face, USB up), 12 through-holes; pin 1 (VBAT) at the top, pin 12 (SDA) at the bottom. The column shares the 27-unit pin pitch and the bottom end with JP1, so VBAT sits level with JP1.12/A0 as in the Adafruit pinout drawing (12 pins)

No.	Name	Type	GPIO	Function
1	VBAT	P		Li-po battery input
2	EN	C		Regulator enable / power switch
3	VBUS	P		USB 5 V
4	D13	I/O	13	GPIO13; ADC2_CH2
5	D12	I/O	12	GPIO12; ADC2_CH1
6	D11	I/O	11	GPIO11; ADC2_CH0
7	D10	I/O	10	GPIO10; ADC1_CH9
8	D9	I/O	9	GPIO9; ADC1_CH8
9	D6	I/O	6	GPIO6; ADC1_CH5
10	D5	I/O	5	GPIO5; ADC1_CH4
11	SCL	I/O	4	GPIO4; ADC1_CH3
12	SDA	I/O	3	GPIO3; ADC1_CH2

Adafruit's Feather ESP32-S3 puts an ESP32-S3 mini-module on the standard Feather footprint: 28 through-holes in two rows — left JP1 16 (RESET at the top down to TXD0 = GPIO43 at the bottom: RST, 3.3V, 3.3V, GND, A0-A5, SCK, MOSI, MISO, RX, TX, TXD0) and right JP3 12 (VBAT, EN, VBUS, D13, D12, D11, D10, D9, D6, D5, SCL, SDA; the column bottom-aligns with JP1, so VBAT sits level with JP1.12/A0) — one USB-C on the chip's native USB, battery pads with a MAX17048 fuel gauge, and one NeoPixel on GPIO33 whose power is gated by GPIO21 — drive GPIO21 HIGH before lighting it. Which of the three SKUs (5323 / 5477 / 5885) fits a project is answered in Which Feather ESP32-S3 should I buy?.

Three buying details matter. First, the board ships as three SKUs of one PCB: 5323 (8 MB flash, no PSRAM), 5477 (4 MB flash + 2 MB PSRAM) and 5885 (8 MB flash, no PSRAM, w.FL antenna connector instead of the PCB antenna) — the pinout and schematic are shared. Second, I2C lives on GPIO3/GPIO4 (not A4/A5 like an AVR Arduino), and the STEMMA QT connector shares that bus; GPIO7 (I2C_POWER) can cut the connector's pull-up power entirely. Third, the analog-labeled pads A0-A5 are ordinary GPIOs — GPIO18/17/16/15/14/8 — and the official pinout names every one.

This page renders the MCUID data record: full header mapping taken from Adafruit's PrettyPins diagram and the JP1/JP3 netlist in the official feather-esp32s3.brd layout file (which adds JP1.1 TXD0/GPIO43), the NeoPixel/battery/STEMMA facts, and every field tied to a fixed vendor source. The Zephyr feather_esp32s3 devicetree corroborates the pins it actually covers; it is a cross-check, not the primary record.