Boardsparkfun

SparkFun Thing Plus ESP32-S3

SparkFun Thing Plus ESP32-S3 (WRL-24408): ESP32-S3R2 N4R2 module on a Feather-compatible board with 28 physical PTH positions carrying 21 GPIO (all silkscreen names mapped to chip IOs from the U10 schematic symbol), Qwiic on IO8/IO9, microSD on SDIO-4 (IO34/38/39/40/47/33), MCP73831 charging + MAX17048 fuel gauge, switchable 3.3V_P rail. The silkscreen 'GPIO0' pad is chip IO21, not IO0.

Assembly & compatibility

Main chip: ESP32-S3

Revisions

v10 (current) — Current revision; the hardware repo's Introduction text and README incorrectly quote 23 GPIO for this board (that number belongs to the C6 variant). · SparkFun Thing Plus ESP32-S3 hardware repo (v10 KiCad schematics; commit 2024-11-15; v10 PDF 2023-07-28 sha256-16 b490fa98) · Hardware/SparkFun_Thing_Plus_ESP32-S3.kicad_sch

Pinout

power · ground · GPIO / signal · onboard LED

Left PTH column, U10 pins 1-12 (v10 board view, USB down; rotating the board on its face to USB up swaps the two columns, pin 1 stays at the USB-near end) (12 pins)

Physical column split per the v10 KiCad U10 symbol - signal and power pads are NOT grouped; left column is U10.1-12, right column U10.13-28 · Source: SparkFun Thing Plus ESP32-S3 hardware repo (v10 KiCad schematics; commit 2024-11-15; v10 PDF 2023-07-28 sha256-16 b490fa98) · Thing Plus ESP32-S3 v10 KiCad, connector U10 left column pins 1-12

No.	Name	Type	GPIO	Function
1	SDA	I/O	8	IO8; I2C data; U10 pin 1; Qwiic connector ties here
2	SCL	I/O	9	IO9; I2C clock; U10 pin 2; Qwiic connector ties here
3	GPIO6	I/O	1	Chip IO1; U10 pin 3
4	GPIO5	I/O	2	Chip IO2; U10 pin 4
5	GPIO4	I/O	4	Chip IO4; U10 pin 5
6	GPIO3	I/O	5	Chip IO5; U10 pin 6
7	GPIO2	I/O	6	Chip IO6; U10 pin 7
8	GPIO1	I/O	7	Chip IO7; U10 pin 8
9	D0	I/O	21	Chip IO21 (silkscreen D0 - not IO0); BOOT/STAT pads are the IO0 pair
10	V_USB	P		USB 5 V from the Type-C port
11	EN	C		3.3 V regulator enable / power control
12	V_BATT	P		Li-po battery input (MCP73831 charge path)

Right PTH column, U10 pins 13-28 (v10 board view, USB down; rotating the board on its face to USB up swaps the two columns, pin 13 stays at the USB-far end) (16 pins)

Numbers are the physical U10 pin numbers 13-28, visible on every row including 26 AREF/NC and the power positions · Source: SparkFun Thing Plus ESP32-S3 hardware repo (v10 KiCad schematics; commit 2024-11-15; v10 PDF 2023-07-28 sha256-16 b490fa98) · Thing Plus ESP32-S3 v10 KiCad, connector U10 right column pins 13-28

No.	Name	Type	GPIO	Function
13	FREEBIE	I/O	42	Spare broken-out pad on IO42; U10 pin 13
14	TX	O	43	UART transmit (U0TXD); U10 pin 14
15	RX	I	44	UART receive (U0RXD); U10 pin 15
16	POCI	I/O	13	IO13; SPI data in; U10 pin 16
17	PICO	I/O	11	IO11; SPI data out; U10 pin 17
18	SCK	I/O	12	IO12; SPI clock; U10 pin 18
19	A5	I/O	18	IO18; analog input; U10 pin 19
20	A4	I/O	17	IO17; analog input; U10 pin 20
21	A3	I/O	16	IO16; analog input; U10 pin 21
22	A2	I/O	15	IO15; analog input; U10 pin 22
23	A1	I/O	14	IO14; analog input; U10 pin 23
24	A0	I/O	10	IO10; analog input; U10 pin 24
25	GND	G		Ground
26	AREF	-		Analog reference pad, not connected in v10 (net AREF/NC)
27	3.3V	P		3.3 V output
28	RST	C		ESP32-S3 EN / reset

Qwiic (JST SH 4-pin) connector (4 pins)

Standard Qwiic pin 1 GND, pin 2 3V3 (switchable 3.3V_P rail), pin 3 SDA, pin 4 SCL. · Source: SparkFun Thing Plus ESP32-S3 hardware overview (PTH headers, Qwiic, uSD, buttons, LP_CTL) · hardware_overview 'Pinout & Qwiic Connector'

No.	Name	Type	GPIO	Function
1	GND	G		Ground
2	3V3	P		3.3V_P switchable peripheral rail
3	SDA	I/O	8	IO8; I2C data (same net as the SDA PTH)
4	SCL	I/O	9	IO9; I2C clock (same net as the SCL PTH)

SparkFun's Thing Plus ESP32-S3 (sold as WRL-24408) is the Feather-footprint ESP32-S3R2 board (N4R2: 4 MB flash + 2 MB PSRAM). Its headers carry 28 physical PTH positions in two U10 columns (left U10.1-12: SDA, SCL, GPIO6-GPIO1, D0, V_USB, EN, V_BATT; right U10.13-28: FREEBIE, TX, RX, POCI, PICO, SCK, A5-A0, GND, AREF, 3.3V, RST — signal and power pads are interleaved, not grouped) — exposing UART 2 (TX/RX), I2C 2 (SDA/SCL, IO8/IO9, with a Qwiic connector), SPI 3 (SCK/PICO/POCI), six analog-labeled pads A0-A5, six pads silkscreened GPIO1-GPIO6 (pad labels, not chip IO numbers — they map to chip IO1/IO2/IO4-IO7), and one FREEBIE pad. A friction-fit microSD slot runs on SDIO-4 (CMD=IO34, CLK=IO38, DAT0-3=IO39/40/47/33 — board-occupied, not on the headers), and a 2-pin JST feeds a MCP73831 charger plus a MAX17048 fuel gauge on I2C.

Every silkscreen name is now mapped to its chip IO via the schematic's U10 symbol: TX=IO43, RX=IO44, SDA=IO8, SCL=IO9, POCI=IO13, PICO=IO11, SCK=IO12, A0-A5=IO10/14/15/16/17/18, D0=IO21 (silkscreen reads D0), GPIO1=IO7, GPIO2=IO6, GPIO3=IO5, GPIO4=IO4, GPIO5=IO2, GPIO6=IO1, FREEBIE=IO42. More onboard loads explain the gap between chip pins and headers: WS2812 RGB LED on IO46, STAT LED sharing chip IO0 with the BOOT button, MAX17048 alert on IO35, and the peripheral-rail enable on IO45. The charge indicator hangs off the MCP73831 charge path and is not a GPIO.

Two traps are recorded on purpose. First, the pad silkscreened D0 (U10.9) is chip IO21 — the BOOT button and the STAT LED both sit on chip IO0 (the BOOT/STAT pad pair) — so writing the silkscreen name as a chip pin number will misconfigure strapping code. Second, SparkFun's own Introduction text and repo README quote 23 GPIO for this board; that number belongs to the Thing Plus ESP32-C6. The sales page (WRL-24408) and the Hardware Overview PTH list both say 28 PTH positions / 21 GPIO, and the v10 schematic's U10 symbol counts 21 signal pins — this record follows those and refuses the C6 value.

A second RT9080 3.3V regulator powers a separate peripheral rail (3.3V_P, Qwiic pull-ups included) governed by the LP_CTL jumper, which is closed by default and ties the enable HIGH. To control the rail from software, cut the jumper first, then drive the enable low — while the jumper is closed the enable stays pulled high and the rail cannot be switched off (per the Hardware Overview jumpers section). This page renders the MCUID data record: both physical U10 columns pad-by-pad with chip IO numbers, the Qwiic connector, and each mapping tied to the fixed schematic source.