The ESP32 is Espressif's classic SoC family: two 32-bit Xtensa LX6 application cores, a 2.4 GHz radio (Wi-Fi and Bluetooth) and an ultra-low-power coprocessor, integrated in the chip. In MCUID's hardware chain — chip → module → board — this page describes what the chip family provides; pins, connectors and flash capacity are decided by the module and the board.
Start from a board: ESP32-DevKitC — the board this site documents for the chip. Official entry: ESP-IDF ESP32 get started.
- Processing — dual Xtensa 32-bit LX6 cores plus an ultra-low-power coprocessor.
- Wireless — 2.4 GHz Wi-Fi and Bluetooth, on-chip.
- USB — the overview list below does not mention native USB for this generation; USB on ESP32 boards is typically a bridge chip, not chip-native USB.
Capabilities — what the chip family provides
Each row is one capability: the official wording, what it means in development, and the source. Clock frequency and the peripheral list belong to the datasheet; the table sticks to what the cited overview states.
Capabilities
| Capability | What the sources say | Source |
|---|---|---|
| Dual-core Xtensa 32-bit LX6 CPU | “Dual high performance Xtensa® 32-bit LX6 CPU cores” (official wording). Application code runs on two identical 32-bit cores; the classic ESP32 generation predates the S3's LX7. | ESP-IDF v6.1 Get Started — ESP32 / ESP32-S3 chip overview · docs/en/get-started/index.rst |
| 2.4 GHz Wi-Fi | “Wi-Fi (2.4 GHz band)” (official wording). Integrated radio — no external Wi-Fi module needed. | ESP-IDF v6.1 Get Started — ESP32 / ESP32-S3 chip overview · docs/en/get-started/index.rst |
| Bluetooth | “Bluetooth” (official wording, unqualified). The source lists plain “Bluetooth” for this chip (unlike the S3's “Bluetooth Low Energy”); no version is added beyond that wording here. | ESP-IDF v6.1 Get Started — ESP32 / ESP32-S3 chip overview · docs/en/get-started/index.rst |
| Ultra-low-power coprocessor | “Ultra Low Power co-processor” (official wording). Keeps small tasks running while the main cores sleep. | ESP-IDF v6.1 Get Started — ESP32 / ESP32-S3 chip overview · docs/en/get-started/index.rst |
| Multiple peripherals | “Multiple peripherals” (official wording). The overview list does not enumerate them; specifics belong to the chip datasheet. Note this list does not mention native USB — on ESP32 boards the USB port is typically a bridge, not chip-native USB. | ESP-IDF v6.1 Get Started — ESP32 / ESP32-S3 chip overview · docs/en/get-started/index.rst |
Before you rely on a capability — scope and limits
- Chip capability is not header availability. Which pins reach a header is module and board wiring.
- Flash capacity is a module fact. Modules like the WROOM-32E and WROVER-E carry the flash; check the module page for storage, not this page.
- USB on the board is a bridge. The DevKitC's micro-USB port goes through a USB-to-UART bridge — flashing and console run over serial, not native USB (a difference from the ESP32-S3 generation).
- Bluetooth wording. The cited overview says plain "Bluetooth" for this chip; this page adds no version or profile set beyond that wording.
Modules and boards built on the ESP32
Module variants and antenna options live on the module pages; pinouts and revisions on the board pages.
Modules using this chip
Boards using this chip
Start developing
- ESP-IDF (official SDK) — the ESP-IDF get-started for ESP32 installs the toolchain and walks through the first project.
- Arduino IDE — the esp32 board package supports the classic ESP32; MCUID's DevKitC first-flash guide covers the single USB port, the no-user-LED trap and the first blink.
- Board in hand but unknown? Read the board page and its identification notes first; GPIO defaults come from the board, not from this chip page.
Common questions this site answers
- First flash on the DevKitC V4 — one USB port, no user LED, the C15 note and three mutually exclusive supply paths.
- The board is not detected over USB — the five-step observable-breakpoint checklist, including the bridge chain this generation uses.
- 3.3 V and 5 V on these boards — power rails and why GPIOs are 3.3 V logic.
Sources and evidence
- Chip capabilities — the table cites the ESP-IDF v6.1 get-started, ESP32 overview section (
docs/en/get-started/index.rst), retrieved 2026-11-09. - Numbers not listed here — clock, SRAM and GPIO count belong to the datasheet; the table sticks to the overview's wording.
- Board and module facts — live on their own pages with their own sources.
Also known as: ESP32D0WD, esp32