BoardWaveshare

Waveshare ESP32-S3-Zero

Waveshare ESP32-S3-Zero board record (SKU 25081/25517, ESP32-S3FH4R2): 4 MB stacked flash + 2 MB Quad SPI PSRAM (datasheet v2.2 Table 1-1, PDF p.13; the vendor page's Octal wording noted), WS2812 RGB on GPIO21, native-USB Type-C with no bridge chip, GPIO33~37 not led out on this PCB, and the pad table in its real grouping: 18 edge + 3 front-inner + 8 back-inner.

Assembly & compatibility

Revisions

Pinout

Waveshare ESP32-S3-ZeroEdge castellated pads, two columns (front, USB up: left 5V/GND/3V3/GP1-GP6, right TX/RX/GP13-GP7)5VGND3V3GP1GP2GP3GP4GP5GP6TXRXGP13GP12GP11GP10GP9GP8GP7Front inner pads (right of the front face, top-to-down)GP16GP15GP14BACK_INNERGP45GP42GP41GP40GP39GP38GP18GP17

power · ground · GPIO / signal · onboard LED

Edge castellated pads, two columns (front, USB up: left 5V/GND/3V3/GP1-GP6, right TX/RX/GP13-GP7) (18 pins)

Physical order from the official pinout image (sha256 0df7f252...), cross-checked against the schematic PDF (sha256 4bbdae93...). Schematic P15 numbers the 18-pad chain 1-18 (1 TX, 2 RX, 3-9 GP13-GP7, 10-15 GP6-GP1, 16 3V3, 17 GND, 18 VBUS): the silk 5V pad is net VBUS on the schematic. EN/BOOT buttons and the on-board USB 19/20 / RGB 21 wiring are not pads — see claims. · Source: Waveshare ESP32-S3-Zero product page, resources page, schematic, pinout · official pinout webp (0df7f252...) cross-checked against schematic PDF (4bbdae93...)

No.NameTypeGPIOFunction
15VPExternal power pad (silk 5V; net VBUS on schematic P15, pad 18), 3.7-6 V
2GNDGGround
33V3P3.3 V regulated output (ME6217C33M5G LDO)
4GP1I/O1GPIO1
5GP2I/O2GPIO2
6GP3I/O3GPIO3
7GP4I/O4GPIO4
8GP5I/O5GPIO5
9GP6I/O6GPIO6
10TXI/O43GPIO43; default UART0 TX (silkscreen TX)
11RXI/O44GPIO44; default UART0 RX (silkscreen RX)
12GP13I/O13GPIO13
13GP12I/O12GPIO12
14GP11I/O11GPIO11
15GP10I/O10GPIO10
16GP9I/O9GPIO9
17GP8I/O8GPIO8
18GP7I/O7GPIO7

Front inner pads (right of the front face, top-to-down) (3 pins)

Physical order from the official pinout image (sha256 0df7f252...), cross-checked against the schematic PDF (sha256 4bbdae93...). Three inner pads, distinct from the edge castellations. · Source: Waveshare ESP32-S3-Zero product page, resources page, schematic, pinout · official pinout webp (0df7f252...) cross-checked against schematic PDF (4bbdae93...)

No.NameTypeGPIOFunction
1GP16I/O16GPIO16
2GP15I/O15GPIO15
3GP14I/O14GPIO14

Back inner pads (back face, USB up, top-to-down) (8 pins)

Physical order from the official pinout image (sha256 0df7f252...), cross-checked against the schematic PDF (sha256 4bbdae93...). Eight inner pads on the board back. · Source: Waveshare ESP32-S3-Zero product page, resources page, schematic, pinout · official pinout webp (0df7f252...) cross-checked against schematic PDF (4bbdae93...)

No.NameTypeGPIOFunction
1GP45I/O45GPIO45
2GP42I/O42GPIO42
3GP41I/O41GPIO41
4GP40I/O40GPIO40
5GP39I/O39GPIO39
6GP38I/O38GPIO38
7GP18I/O18GPIO18
8GP17I/O17GPIO17

The Waveshare ESP32-S3-Zero is an ultra-compact castellated board built on the ESP32-S3FH4R2 (4 MB flash + 2 MB PSRAM stacked in the chip package). This page renders the MCUID data record: identity, the on-board resources, and the pads verified against fixed sources, in their real grouping (18 edge + 3 front-inner + 8 back-inner).

Identify your board

Third-party compact board vs official DevKit

Waveshare documents this board through its own wiki and product pages, which remain vendor-official one-hand sources, but the documentation depth differs from Espressif's own DevKit guides: no per-revision user guide, no Espressif board-level support policy. If you need the full official-guide treatment (numbered headers, boot-mode tables, power-path details), the ESP32-S3-DevKitC-1 or the EOL ESP32-S3-DevKitM-1 records cover those boards. This record sticks to what Waveshare actually publishes.

One Type-C port, no USB-to-UART chip

The board does not employ a USB-to-UART chip: the Type-C port is wired straight to the ESP32-S3's native USB. Flashing uses the chip's ROM/USB download flow — hold BOOT (GPIO0) while plugging the cable, then flash. The silkscreen TX/RX pads are GPIO43/GPIO44 (default UART0) for serial consoles.

On-board RGB LED — GPIO21

A WS2812 addressable RGB LED driven by GPIO21 — wired on-board, not an edge pad. Driving GPIO21 high/low does not produce colors — an addressable-LED protocol is required.

Power

USB powers the board through an ME6217C33M5G LDO (max 800 mA). For standalone use, feed 3.7 V~6 V into the castellated hole marked 5V — outside that range the LDO is out of spec.

Pin data status — 18 edge + 3 front-inner + 8 back-inner

The pad tables below follow the official pinout image's real physical grouping. 18 edge castellated pads in two columns (front, USB up: left 5V/GND/3V3/GP1–GP6, right TX/RX/GP13–GP7), 3 front inner pads (GP16/GP15/GP14, top-to-down to the right of the front face), and 8 back inner pads (GP45/GP42/GP41/GP40/GP39/GP38/GP18/GP17, back face USB up). The schematic numbers the 18-pad chain 1–18 (P15: 1 TX … 16 3V3, 17 GND, 18 VBUS) — the silk 5V pad is net VBUS on the schematic. USB D−/D+ (GPIO19/20), the RGB DIN (GPIO21) and BOOT (GPIO0) are wired on-board and are not pads — see the claims above.

Start developing

Common questions this site answers

Also known as: esp32-s3-zero, esp32-s3-zero-m, s3 zero